Publications

Papers

  1. Boma A. Adhi, Masayoshi Mase, Yuhei Hosokawa, Yohei Kishimoto, Taisuke Onishi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Software Cache Coherent Control by Parallelizing Compiler", 30th International Workshop on Languages and Compilers for Parallel Computing(LCPC), Oct. 2017.
  2. Hironori Kasahara, Keiji Kimura, Boma A. Adhi, Yuhei Hosokawa,Yohei Kishimoto, Masayoshi Mase, "Multicore Cache Coherence Control by a Parallelizing Compiler", IEEE COMPSAC 2017 (The 41th IEEE Computer Society International Conference on Computers, Software & Applications), Jul. 2017.
  3. Koichiro Yamashita, Takahisa Suzuki, Hongchun Li, Chen Ao, Yi Xu, Jun Tian, Keiji Kimura, Hironori Kasahara, "Architecture Design for the Environmental Monitoring System over the Winter Season", Proc. of the 14th ACM International Symposium on Mobility Management and Wireless Access, pp. 27--34, Nov., 2016.
  4. Jixin Han, Rina Fujino, Ryota Tamura, Mamoru Shimaoka, Hiroki Mikami, Moriyuki Takamura, Sachio Kamiya, Kazuhiko Suzuki, Takahiro Miyajima, Keiji Kimura, and Hironori Kasahara, "Reducing Parallelizing Compilation Time by Removing Redundant Analysis", The 3rd International Workshop on Software and Engineering for Parallel Sysmtems (SEPS 2016), Nov. 2016.
  5. Kouhei Yamamoto, Tomoya Shirakawa, Yoshitake Oki, Akimasa Yoshida, Keiji Kimura and Hironori Kasahara, "Automatic Local Memory Management for Multicores Having Global Address Space", The 29th International Workshop on Languages and Compilers for Parallel Computing(LCPC), Oct. 2016.
  6. Lau Phi Tuong, Keiji Kimura, "2-Step Power Scheduling with Adaptive Control Interval for Network Intrusion Detection Systems on Multicores", 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Sep. 2016.
  7. Keiji Kimura, Gakuho Taguchi, Hironori Kasahara, "Accelerating Multicore Architecture Simulation Using Application Profile", 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Sep. 2016.
  8. Bui Duc Binh, Keiji Kimura, "An Android Systrace Extension for Tracing Wakelocks", 2016 IEEE International Conference on Embedded and Ubiquitous Computing (EUC 2016), pp.146-149, Aug. 2016.
  9. Bui Duc Binh, Tomohiro Hirano, Hiroki Mikami, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara, "Android Video Processing System Combined with Automatically Parallelized and Power Optimized Code by OSCAR Compiler", Journal of Information Processing (online), Vol. 24, No. 3, pp.504-511, May. 2016.
  10. Reem Elkhouly, Keiji Kimura, Ahmed El-Mahdy, "If-Conversion Optimization using Neuro Evolution of Augmenting Topologies", CoRR abs/1603.01112 (2016)
  11. Dan Umeda, Takahiro Suzuki, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Multigrain Parallelization Using Profile Information of Embedded Applications Generated by Model-based Development Tools on Multicore Processors", Trans. of IPSJ, Vol. 57, No. 2, pp.1-12, Feb. 2016
  12. Daichi Fukui, Mamoru Shimaoka, Hiroki Mikami, Dominic Hillenbrand, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara, "Annotatable Systrace: An Extended Linux ftrace for Tracing a Parallelized Program", The 2nd International Workshop on Software and Engineering for Parallel Sysmtems (SEPS 2015), Oct. 2015.
  13. Mamoru Shimaoka, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various cc-NUMA Servers", The 28th International Workshop on Languages and Compilers for Parallel Computing(LCPC),Sep.2015.
  14. Dan Umeda, Takahiro Suzuki, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Multigrain Parallelization for Model-based Design Applications Using the OSCAR Compiler", The 28nd International Workshop on Languages and Compilers for Parallel Computing (LCPC), Sep.2015.
  15. Dan Umeda, Youhei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Mituhiro Tani (DENSO), Yuji Mori (DENSO), Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Designed Engine Control C Codes by MATLAB/Simulink", Trans. of IPSJ,ol. 55, No. 8, pp.1817-1829, Aug.2014.
  16. Tomohiro Hirano, Hideo Yamamoto, Shuhei Iizuka, Kohei Muto, Takashi Goto, Tamami Wake, Hiroki Mikami, Moriyuki Takamura, Keiji Kimura,Hironori Kasahara, "Evaluation of Automatic Power Reduction with OSCAR Compiler on Intel Haswell and ARM Cortex-A9 Multicores", The 27th International Workshop on Languages and Compilers for Parallel Computing(LCPC), Sep. 2014.
  17. Keiji Kimura, Hironori Kasahara, "Multicore Technologies Realizing Low-Power Computing", The Journal of IEICE, pp.133-139, Vol. 97, No. 2, Feb. 2014.
  18. Hideo Yamamoto, Tomohiro Hirano, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Moriyuki Takamura, Keiji Kimura, and Hironori Kawahara, "OSCAR Compiler Controlled Multicore Power Reduction on Android Platform", The 26th International Workshop on Languages and Compilers for Parallel Computing,(LCPC2013), Qualcomm Research Silicon Valley, US, Sep. 2013.
  19. Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura and Hironori Kasahara, "Reconciling Application Power Control and Operating Systems for Optimal Power and Performance", 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC (ReCoSoC2013), Darmstadt, Germany, Jul. 2013.
  20. Dan Umeda, Yohei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Hand Written Automotive Engine Control Codes Using OSCAR Compiler", 17th Workshop on Compilers for Parallel Computing (CPC2013), Lyon, France, Jul. 2013. (PDF)
  21. Keiji Kimura, Cecilia Gonzales-Alvarez, Akihiro Hayashi, Hiroki Mikami, Mamoru Shimaoka, Jun Shirako, Hironori Kasahara, "OSAR API v2.1: Extensions for an Advanced Accelerator Control Scheme to a Low-Power Multicore API", 17th Workshop on Compilers for Parallel Computing (CPC2013), Lyon, France, Jul. 2013. (PDF)
  22. Dominic Hillenbrand, Akihiro Hayashi, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization, Performance Predictability and Power Control for Mobile-Applications", COOL Chips XVI, IEEE Symposium on Low Power and High-Speed Chips, Apr. 2013.
  23. Yohei Kanehagi, Dan Umeda, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "Parallelization of Automotive Engine Control Software On Embedded Multi-core Processor Using OSCAR Compiler", COOL Chips XVI, IEEE Symposium on Low Power and High-Speed Chips, Apr. 2013.
  24. Cecilia Gonzalez-Alvarez, Haruku Ishikawa, Akihiro Hayashi, Daniel Jimenez-Gonzalez, Carlos Alvarez, Keiji Kimura, Hironori Kasahara, "Automatic Design Exploration Framework for Multicores with Reconfigurable Accelerators", 7th Workshop on Reconfigurable Computing (WRC) 2013, held in conjuction with HiPEAC conference 2013, Berlin, Jan. 2013.
  25. Yasir I Al-Dosary, Keiji Kimura, Hironori Kasahara, and Seinosuke Narita, "Enhancing the Performance of a Multiplayer Game by Using a Parallelizing Compiler", 17th International Conference on Computer Games: AI, Animation, Mobile, Educational & Serious Games, Jul. 2012.
  26. Akihiro Hayashi, Mamoru Shimaoka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Jun Shirako, Keiji Kimura, and Hironori Kasahara, "OSCAR Parallelizing Compiler and API for Real-time Low Power Heterogeneous Multicores", 16th Workshop on Compilers for Parallel Computing(CPC2012), Padova, Italy, Jan. 2012.
  27. Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura and Hironori Kasahara, "Parallelizing Compiler Framework and API for Heterogeneous Multicores", IPSJ Transactions on Advanced Computing Systems, Vol.5, No.1, pp.68-79,Nov. 2011. (PDF)
  28. Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, and Hironori Kasahara, "A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture", Transactions on High-Performance Embedded Architectures and Compilers IV, ecture Note in Computer Science, Springer, Vol. 6760, pp.215-233, Nov. 2011.
  29. Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, and Hironori Kasahara, "Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-power Multicore", Proc. of LCPC 2011(The 24th International Workshop on Languages and Compilers for Parallel Computing ) , Colorado State University, Fort Collins, Colorado, Sept 8-10, 2011. (PDF)
  30. Osamu NISHII, Yoichi YUYAMA, Masayuki ITO, Yoshikazu KIYOSHIGE, usuke NITTA, Makoto ISHIKAWA, Tetsuya YAMADA, Junichi MIYAKOSHI, YasutakaWADA, Keiji KIMURA, Hironori KASAHARA, and Hideo MAEJIMA, "A 45-nm37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core", IEICE TRANSACTIONS on Electronics, Vol. E94-C, No. 4,pp.663-669, Apr. 2011.
  31. A. Hayashi, Y. Wada, T. Watanabe, T. Sekiguchi, M. Mase, J. Shirako, K. Kimura, H. Kasahara, "Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-time Heterogeneous Multicores", Lecture Notes in Computer Science, Springer, Vol. 6548, pp.184-198, Feb., 2011
  32. A. Hayashi, Y. Wada, T. Watanabe, T. Sekiguchi, M. Mase, J. Shirako, K. Kimura, H. Kasahara, "Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-time Heterogeneous Multicores", Proc. of The 23rd International Workshop on Languages and Compilers for Parallel Computing (LCPC2010), Oct. 2010.
  33. Keiji Kimura, Masayoshi Mase, Hiroki Mikami, Takamichi Miyamoto, Jun Shirako and Hironori Kasahara, "OSCAR API for Real-time Low-Power Multicores and Its Performance on Multicores and SMP Servers", Lecture Notes in Computer Science, Springer, Vol. 5898, pp. 188-202, 2010
  34. Masayoshi Mase, Yuto Onozaki, Keiji Kimura, Hironori Kasahara, "Parallelizable C and Its Performance on Low Power High Performance Multicore Processors", Proc. of 15th Workshop on Compilers for Parallel Computing (CPC 2010), Jul., 2010
  35. Takumi Nito, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Takada, Makoto Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, and Hideo Maejima,"A 45nm Heterogeneous Multi-core SoC Supporting an over 32-bits Physical Address Space for Digital Appliance", Proc. of IEEE Symposium on Low-Power and High Speed Chips (COOL Chips XIII), Apr. 2010.
  36. Y. Yuyama, M. Ito, Y. Kiyoshige, Y. Nitta, S. Matsui, O.Nishii, A. Hasegawa, M. Ishikawa, T. Yamada, J. Miyakoshi, K. Terada, T. Nojiri, M. Satoh, H. Mizuno, K. Uchiyama, Y. Wada, K. Kimura, H.Kasahara, H. Maejima, "A 45nm 37.3GOPS/W Heterogeneous Multi-Core SoC", 2010 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCCf2010), San Francisco, Feb. 8, 2010.
  37. Masayoshi Mase, Yuta Murata, Keiji Kimura, Hironori Kasahara, "Element-Sensitive Pointer Analysis for Automatic Parallelization", IPSJ Transactions on Programming (PRO), Vol. 3, No. 2, pp. 36--47, Mar., 2010.
  38. Keiji Kimura, Masayoshi Mase, Hiroki Mikami, Takamichi Miyamoto, Jun Shirako and Hironori Kasahara, "OSCAR API for Real-time Low-Power Multicores and Its Performance on Multicores and SMP Servers", Proc. of The 22nd International Workshop on Languages and Compilers for Parallel Computing (LCPC2009), Oct. 2009.
  39. Masafumi Onouchi, Keisuke Toyama, Toru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara, "Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme" (link), Proc. of 2009 International Conference on Parallel Processing, pp. 510-517, September 22-September 25, 2009, AustriaVienna.
  40. Masayoshi Mase, Ryo Nakagawa, Naoto Ohkuni, Jun Shirako, Keiji Kimura, Hironori Kasahara, "A Power Reduction Scheme of Parallelizing Compiler Using OSCAR API on Multicore Processor", Trans. of IPSJ on Computing Systems, Vol. 2, No. 3, pp.96-106, Sep. 2009.
  41. Hirofumi Nakano, Taku Momozono, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Local Management Scheme by a Compiler on a Multicore Processor for Coarse Grain Task Parallel Processing", IPSJ Transactions on Advanced Computing Systems, Vol. 2, No. 2, pp.63-74, Jul. 2009.
  42. Hiroki Mikami, Jun Shirako, Masayoshi Mase, Takamichi Miyamoto, Hirofumi Nakano, Fumiyo Takano, Akihiro Hayashi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on Multicore Processors", Proc. of 14th Workshop on Compilers for Parallel Computing(CPC 2009), Jan. 2009.
  43. Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API", Proc. of IEEE International Symposium on Advances in Parallel and Distributed Computing Techniques (APDCT-08), Dec. 2008.
  44. Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "An Evaluation of Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API", IPSJ Transactions on Advanced Computing Systems, Vol. 1, No. 3, pp.83-95, Dec. 2008.
  45. Jun Shirako, Keiji Kimura, Hironori Kasahara, "Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler", Proc. of International SoC Design Conference (ISOCC 2008), Nov. 2008.
  46. Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallelization of MP3 Encoder using Static Scheduling on a Heterogeneous Multicore", Trans. of IPSJ on Computing Systems, Vol. 1, No. 1, pp.105-119, Jun. 2008.
  47. Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Parallelizing Compiler Cooperative Heterogeneous Multicore", Proc. of Workshop on Software and Hardware Challenges of Manycore Platforms (SHCMP 2008), Jun. 2008.
  48. Yutaka Yoshida, Masayuki Ito, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Toshihiro Hattori, Jun Sakiyama, Masashi Takada, Kunio Uchiyama, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "An 8 CPU SoC with Independent Power-off Control of CPUs and Multicore Software Debug Function", Proc. of IEEE Cool Chips XI: Symposium on Low-Power and High-Speed Chips 2008, Apr. 2008.
  49. Hiroaki Shikano, Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Heterogeneous Multi-core Architecture that Enables 54x AAC-LC Stereo Encoding", IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp.902-910, Apr. 2008.
  50. Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Power-Aware Compiler Controllable Chip Multiprocessor", IEICE TRANS. ELECTRON, Vol. E91-C, No. 4, pp.432-439, Apr. 2008.
  51. Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Masaki Ito, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "A 600MHz SoC with Compiler Power-off Control of 8 CPUs and 8 Onchip-RAMs", Proc. of International Solid State Circuits Conference (ISSCC2008), pp.90-91, Feb. 2008.
  52. Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Software-Cooperative Power-Efficient Heterogeneous Multi-Core for Media Processing", Proc. of 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp.736-741, Jan. 2008.
  53. Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Compiler Controlled Power Saving Scheme", Lecture Notes in Computer Science, Springer, Vol. 4759, pp.480-493, Jan. 2008.
  54. Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Hiroshi Tanaka, Tomoyuki Kodama, Hiroaki Shikano, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Heterogeneous Multiprocessor on a Chip Which Enables 54x AAC-LC Stereo Encoding", Proc. of 2007 Symposia on VLSI TEchnology and Circuits, Jun. 2007.
  55. Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura and Hioronori Kasahara, "Performance Evaluation of MP3 Audio Encoder on OSCAR Heterogeneous Chip Multicore Processor", Trans. of IPSJ on Computing Systems, Vol. 48, No. SIG8(ACS18), pp.141-152, May. 2007.
  56. Jun Shirako, Nato Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving Scheme for Multi Core Processors", Lecture Notes in Computer Science, Springer, Vol. 4339, pp.362-376, May. 2007.
  57. Y. Yoshida, T. Kamei, K. Hayase, S. Shibahara, O. Nishii, T. Hattori, A. Hasegawa, M. Takada, N. Irie, K. Uchiyama, T. Odaka, K. Takada, K. Kimura, H. Kasahara, "A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption", 2007 IEEE International Solid-State Circuits Conference(ISSCC2007), pp.100-101, Feb. 2007.
  58. Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving Scheme for Multicore Processors", Trans. of IPSJ on Computing Systems, Vol. 47(ACS15), 2006. (pdf)
  59. Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Compiler Controlled Power Saving Scheme", Proc. of 20th ACM International Conference on Supercomputing Workshop on Advanced Low Power Systems(ALPS2006), Jul. 2006. (pdf)
  60. Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder", Proc. of IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips IX), pp. 349--363, Apr., 2006,
  61. Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Parallelizing Compilation Scheme for Reduction of Power Consumption of Chip Multiprocessors", Proc. of 12th Workshop on Compilers for Parallel Computers (CPC 2006), Jan. 2006.
  62. Hironori Kasahara, Keiji Kimura, "Multicores Emerge as Next Generation Microprocessors", IPSJ MAGAZINE, Vol. 47, No. 1, pp. 10--16, Jan., 2006.
  63. Keiji Kimura, "Programing for Multicore Systems", IPSJ MAGAZINE, Vol. 47, No. 1, pp. 17--23, Jan., 2006.
  64. Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving Scheme for Multi Core Processors", Proc. of The 18th International Workshop on Languages and Compilers for Parallel Computing (LCPC2005), Oct. 2005.
  65. Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallel Processing of MPEG2 Encoding on a Chip Multiprocessor Architecture", Trans. of IPSJ, Vol. 46, No. 9, pp.2311-2325, Sep. 2005.
  66. Kazuhisa Ishizaka, Takamichi Miyamoto, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers", Lecture Notes in Computer Science , Vol. 3602, pp.319, 2005
  67. Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara, "Multigrain Parallel Processing on Compiler Cooperative Chip Multiprocessor", Proc. of 9th Workshop on Interaction between Compilers and Computer Architectures (INTERACT-9), pp.11-20, Feb., 2005
  68. Kazuhisa Ishizaka, Takamichi Miyamoto, Jun Shirako, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers", Proc. of 17th International Workshop on Languages and Compilers for Parallel Computing (LCPC2004), Sep., 2004
  69. Keiji Kimura, Takeshi Kodaka, Motoki Obata, Hironori Kasahara, "Multigrain Parallel Processing on Compiler Cooperative OSCAR Chip Multiprocessor Architecture", The IEICE Transactions on Electronics, Special Issue on High-Performance and Low-Power System LSIs and Related Technologies, pp. 570--579, Vol. E86-C, No. 4, Apr., 2003. IEICE Transactions ONLINE
  70. Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara , "Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP", International Journal of Parallel Programming, June 2003, Volume 31, Issue 3, pp. 211-223. (pdf)
  71. Takeshi Kodaka, Hirohumi Nakano, Keiji Kimura and Hironori Kasahara, "Parallel Processing using Data Localization for MPEG2 Encoding on OSCAR Chip Multiprocessor", Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04), Jan., 2004. (pdf)(long paper will be appeared later)
  72. Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara, "Memory Management for Data Localization on OSCAR Chip Multiprocessor", Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04), Jan., 2004. (pdf)(long paper will be appeared later)
  73. Keiji Kimura, Takeshi Kodaka, Motoki Obata, Hironori Kasahara, "Multigrain Parallel Processing on OSCAR CMP", Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03), pp. 56--65, Jan., 2003.
  74. Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka, Keiji Kimura, Hiroki Kaminaga, Hirofumi Nakano,Kouhei Nagasawa, Akiko Murai, Hiroki Itagaki, Jun Shirako "Performance of Multigrain Parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler", Proc. of 10th International Workshop on Compilers for Parallel Computers (CPC) Amsterdam, Netherland, January 2003.
  75. Takeshi Kodaka, Takayuki Uchida, Keiji Kimura, Hironori Kasahara, "JPEG Encoding Using Multigrain Parallel Processing on a Single Chip Multiprocessor", Trans. of IPSJ on High Performance Computing Systems, pp. 153--162, Vol. 43, No. Sig. 6 (HPS5), 2002
  76. K. Kimura, T. Kato, H. Kasahara, "Evaluation of Processor Core Architecture for Single Chip Multiprocessor with Near Fine Grain Parallel Processing", Trans. of IPSJ, pp. 692--703, Vol. 42, No. 4, Apr., 2001. (pdf)
  77. Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara, "Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP", Springer Lecture Notes in Computer Science 2327 High Performance Computing (Proc. of ISHPC WOMPEI), pp. 479--489, 2002. (pdf)
  78. T. Kodaka, K. Kimura, H. Kasahara, "Multigrain Parallel Processing for JPEG Encoding on a Single Chip Multiprocessor" IEEE Computer Society Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'02), pp. 57--63, Jan., 2002. (pdf)
  79. K. Kimura, H. Kasahara, "Evaluation of Single Chip Multiprocessor Core Architecture with Near Fine Grain Parallel Processing" Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'01), Jan., 2001. (pdf)
  80. K. Kimura, W. Ogata, M. Okamoto, H. Kasahara, "Near Fine Grain Parallel Processing on Single Chip Multiprocessors", Trans. of IPSJ, pp. 1924--1934, Vol.40, No.5, May., 1999. (pdf)
  81. K. Kimura, H. Kasahara, "Near Fine Grain Parallel Processing Using Static Scheduling on Single Chip Multiprocessors", Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'99), IEEE Computer Society, pp. 23--31, Nov., 1999 (pdf)
  82. A. Yoshida, Y. Ujigawa, M. Obata, K. Kimura, and H. Kasahara, "Data-Localization among Doall and Sequential Loops in Coarse Grain Parallel Processing", Seventh Workshop on Compilers for Parallel Computers, Linkoping, Sweden, pp. 266-277, Jun. 29 -Jul. 1 1998.
  83. H. Kasahara, M. Okamoto, A. Yoshida, W. Ogata, K. Kimura, G. Matsui, H. Matsuzaki, H.Honda "OSCAR Multi-grain Architecture and Its Evaluation", Proc. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, (IWIA'97), IEEE Computer Society, pp. 106--115, Oct. 1997.
  84. W. Ogata, A. Yoshida, M. Okamoto, K. Kimura, H. Kasahara, "Near Fine Grain Parallel Processing without Explicit Synchronization on a Multiprocessor System", Proc. of Sixth Workshop on Compilers for Parallel Computers (Aachen, Germany), Dec. 1996.

Invited Talks

  1. Keiji Kimura, "A Latency Reduction Technique for Network Intrusion Detection System on Multicores", 14th International Forum on Embedded MPSoC and Multicore, Margaux, France, Jul. 8. 2014.
  2. Keiji Kimura, "OSCAR API v2.1 with Flexible Accelerator Control Facilities", 13th International Forum on Embedded MPSoC and Multicore, Otsu, Japan, Jul. 18. 2013.
  3. Keiji Kimura, "OSCAR API for Low-Power Multicores and Manycores, and API Standard Translator", 12th International Forum on Embedded MPSoC and Multicore, Quebec, Canada, Jul. 11. 2012.
  4. Keiji Kimura, "OSCAR Multigrain Parallelizing Compiler and Low-Power Multicore API", International Embedded Multi-core Workshop, ITRI, Taiwan, Nov., 17, 2008

Symposium

  1. Dan Umeda, Youhei Kanehagi, Hiroki Mikami, Mitsuhiro Tani(DENSO), Yuji Mori(DENSO), Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Automatically Generated Engine Control C Codes by Model-based Design", Embedded System Symposium2013, pp.104-113, Oct. 2013.
  2. Yohei Kishimoto, Hiroki Mikami, Keiichi Nakano, Akihiro Hayashi, Keiji Kimura and Hironori Kasahara, "Parallel processing of multimedia applications on TILEPro64 using OSCAR API for embedded multicore", Embedded System Symposium2012, Oct. 2012.
  3. Akihiro Hayashi, Takuji Matsumoto, Hiroki Mikami, Keiji Kimura, Keiji Yamamoto, Hironori Saki, Yasuyuki Takatani and Hironori Kasahara, "Automatic Parallelization of Dose Calculation Engine for A Particle Therapy", Symposium on High-Performance Computing and Computer Science(HPCS2012), Jan. 2012.
  4. Ryo Nakagawa, Masayoshi Mase, Naoto Ohkuni, Jun Shirako, Keiji Kimura, Hironori Kasahara, "A Power Reduction Scheme of Parallelizing Compiler Using OSCAR API on Multicore Processor", Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2009), May. 2009.
  5. Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Parallelization of Multimedia Applications by Compiler on Multicores for Consumer Electronics", Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2008), May. 2008. pdf
  6. Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving Scheme for Multicore Processors", Proc. of Symposium on Advanced Computing Systems and Infrastructures (SACSIS2006), pp. 467--476, May., 2006.
  7. Takeshi Kodaka, Takayuki Uchida, Keiji Kimura, Hironori Kasahara, "JPEG Encoding using Multigrain Parallel Processing on a Shingle Chip Multiprocessor", Joint Symposium on Parallel Processing 2002 (JSPP2002), May., 2002.

Technical Reports

  1. Gakuho Taguchi, Keiji Kimura, Hironori Kasahara, "A Parallelizing Compiler Cooperative Acceleration Technique of Multicore Architecture Simulation using a Statistical Method", IPSJ SIG Technical Report, Mar. 2014.
  2. Shohei Yamada, Keiji Kimura, Hironori Kasahara, "A Latency Reduction Technique for IDS by Allocating Decomposed Signature on Multi-core", IPSJ SIG Technical Report Vol.2013-ARC-201, Mar. 2014.
  3. Yuuki Furuyama, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Small Point FFT on Multicore Processor", IPSJ SIG Technical Report Vol.2013-ARC-201, Mar. 2014.
  4. Takashi Goto, Kohei Muto, Hideo Yamamoto, Tomohiro Hirano, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Profile-Based Automatic Parallelization for Android 2D Rendering by Using OSCAR Compiler", Technical Report of IPSJ, Vol.2013-ARC-207 No.12, Dec. 2013.
  5. Tomohiro Hirano, Hideo Yamamoto, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara, "Automatic Power Control on Multicore Android Devices", Summer Workshops on Parallel, Distributed and Cooperative Processing, Technical Report of IPSJ, Vol.2013-ARC-206 No.23, Aug. 2013.
  6. Akihiro Kawashima, Yohei Kanehagi, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "An Evaluation of Hardware Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping using OSCAR API Standard Translator", Summer Workshops on Parallel, Distributed and Cooperative Processing, Technical Report of IPSJ, Vol.2013-ARC-206 No.16, Aug. 2013.
  7. Yasir I. M. Al-Dosary, Yuki Furuyama, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara, Seinosuke Narita, "Enhancing the Performance of a Multiplayer Game by Using a Parallelizing Compiler", Technical Report of IPSJ, Apr. 2013.
  8. Hideo Yamamoto, Takashi Goto, Tomohiro Hirano, Kouhei Muto, Hiroki Mikami, Dominic Hillenbrand, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "An Investigation of Parallelization and Evaluation on Commercial Multi-core Smart Device", Technical Report of IPSJ, Vol. 2013-OS-124 No. 000310, Feb. 2013.
  9. Gakuho Taguchi, Yoichi Abe, Keiji Kimura, Hironori Kasahara, "A Parallelizing Compiler Cooperative Multicore Architecture Simulator with Changeover Mechanism of Simulation Modes", Technical Report of IPSJ, Vol.2012-ARC-203 N0.14, Jan. 2013.
  10. Yoichi Abe, Gakuho Taguchi, Keiji Kimura, Hironori Kasahara, "An Acceleration Technique of Many-core Architecture Simulation with Parallelized Applications by Statistical Technique", Technical Report of IPSJ, Vol.2012-ARC-203 N0.13, Jan. 2013.
  11. Youhei Kanehagi, Dan Umeda, Hiroki Mikami, Akihiro Hayashi, Mitsuo Sawada(TOYOTA), Keiji Kimura, Hironori Kasahara, "Parallelization of Automobile Engine Control Software on Multicore Processor", Technical Report of IPSJ, Vol.2013-ARC-203 No.2, Jan. 2013.
  12. Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Opportunities and Challenges of Application-Power Control in the Age of Dark Silicon", Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.26, Dec. 2012.
  13. Mamoru Shimaoka, Hiroki Mikami, Akihiro Hayashi, Yasutaka Wada, Keiji Kimura, Hidekazu Morita (HITACHI), Kunio Uchiyama (HITACHI), Hironori Kasahara, "Automatic Parallelization of Ground Motion Simulator", Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.11, Dec. 2012.
  14. Cecilia Gonzalez-Alvarez, Youhei Kanehagi, Kosei Takemoto, Yohei Kishimoto, Kohei Muto, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "Automatic parallelization with OSCAR API Analyzer: a cross-platform performance evaluation", Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.10, Dec. 2012.
  15. Yuuki Furuyama, Mamoru Shimaoka, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "Realization of 1 Watt Web Service with RP-X Low-power Multicore Processor", Technical Report of IPSJ, Vol.2012-ARC-201 No.24, Aug. 2012
  16. Dan Umeda, Youhei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Mituhiro Tani, Yuji Mori, Keiji Kimura, Hironori Kasahara, "Parallelization of Basic Engine Controll Software Model on Multicore Processor", Technical Report of IPSJ, Vol.2012-ARC-201 No.22, Aug. 2012.
  17. Yoichi Abe, Ryo Ishizuka, Ryota Daigo, Gakuho Taguchi, Keiji Kimura, Hironori Kasahara, "An Examination of Accelerating Many-core Architecture Simulation for Parallelized Media Applications", Technical Report of IPSJ, Vol. 2012-ARC-199, No. 3, Mar. 2012.
  18. Keiichi Tabata, Keiji Kimura, Hironori Kasahara, "Inlining Analysis of Exception Flow and Fast Method Dispatch on Automatic Parallelization of Java", Technical Report of IPSJ, Vol. 2012-ARC-199, No. 9, Mar. 2012.
  19. Keiji Kimura, Masayoshi Mase, Hironori Kasahara, "A Definition of Parallelizable C by JISX0180:2011 - Framework of establishing coding guidelines for embedded system development", ETNET2012, Mar. 2012.
  20. Akihiro Hayashi, Takuji Matsumoto, Hiroki Mikami, Keiji Kimura, Keiji Yamamoto, Hironori Saki, Yasuyuki Takatani and Hironori Kasahara, "Automatic Parallelization of Dose Calculation Engine for A Particle Therapy on SMP Servers", Technical Report of IPSJ, Vol.2011-ARC189HPC132-2, Nov. 2011.
  21. Ryo Ishizuka, Yoichi Abe, Ryota Daigo, Keiji Kimura, Hironori Kasahara, "An Evaluation of an Acceleration method of Many-core Architecture Simulation using Program Structures of Scientific Applications", Technical Report of IPSJ, 2011-ARC-196-14, July., 2011.
  22. Yuki Taira, Keiji Kimura, Hironori Kasahara, "Examination of Parallelization by CUDA in SPEC Benchmark Programs", Technical Report of IPSJ, 2011-HPC-130-16, July., 2011
  23. Akihiro Hayashi, Takeshi Sekiguchi, Masayoshi Mase, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Hiding I/O overheads with Parallelizing Compiler for Media Applications", Technical Report of IPSJ, 2011-ARC-195-14, Apr., 2011.
  24. Hiroki Mikami, Shumpei Kitaki, Takafumi Sato, Masayoshi Mase, Keiji Kimura, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro, Hironori Kasahara, "Evaluation of Power Consumption by Executing Media Applications on Low-power Multicore RP2", Technical Report of IPSJ, 2011-ARC-194-1, Mar. 2011.
  25. Takuya Sato, Hiroki Mikami, Akihiro Hayashi, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Evaluation of Parallelizable C Programs by the OSCAR API Standard Translator", Technical Report of IPSJ, 2010-ARC-191-2, Oct., 2010.
  26. Akihiro Hayashi, Yasutaka Wada, Takehi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Keiji Kimura, Masayuki Ito, Atsuhi Hasegawa, Makoto Sato, Tohru Nojiri, Kunio Uchiyama, Hironori Kasahara, "A compiler Framework for Heterogeneous Multicores for Cousumer Electronics", Technical Report of IPSJ, 2010-ARC-190 No. 7, Aug., 2010.
  27. Yasutaka Wada, Akihiro Hayashi, Takehi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Masayuki Ito, Atsuhi Hasegawa, Makoto Sato, Tohru Nojiri, Kunio Uchiyama, Hironori Kasahara, "Performance of Power Reduction on Heterogeneous Multicore for Consumer Electronics RP-X", Technical Report of IPSJ, 2010-ARC-190 No. 8, Aug., 2010.
  28. Ryo Ishizuka, Toshiya Ootomo, Ryota Daigo, Keiji Kimura, Hironori Kasahara, "An Acceleration Technique of Many Core Architecture Simulator Considering Program Structure", Technical Report of IPSJ, 2010-ARC-190 No. 20, Aug., 2010.
  29. Takamichi Miyamoto,Masayoshi Mase, Keiji Kimura,Kazuhisa Ishizaka,Junji Sakai, Masato Edahiro, "Processing Performance of Automatically Parallelized Applications on Embedded Multicore with Running Multiple Applications", Technical Report of IPSJ, 2010-ARC-188 No.9, Mar. 2010.
  30. Hiroki Mikami, Takamichi Miyamoto, Keiji Kimura, Hironori Kasahara, "Hierarchical Parallel Processing of H.264/AVC Encoder on an Multicore Processeor", Technical Report of IPSJ Vol.2010-ARC-187 No.22 Vol.2010-EMB-15 No.22, Jan. 2010.
  31. Masayoshi Mase, Yuta Murata, Keiji Kimura, Hironori Kasahara, "Element-Sensitive Pointer Analysis for Automatic Parallelization", IPSJ-SIGPRO, Oct. 29, 2009.
  32. Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Parallelizable C Programs on Multicore Processors", Technical Report of IPSJ, 2009-ARC-184-15(SWoPP2009), Aug. 2009.
  33. Mamoru Shimaoka, Kazuhiro Imaizumi, Fumiyo Takano, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Minimum Execution Time Multiprocessor Scheduling Algorithms Using Standard Task Graph Set Ver3 Consider Parallelism of Task Graphs and Deviation of Task Execution Time", Technical Report of IEICE, Feb. 2009.
  34. Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/140), Jan. 2009.
  35. Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Local Memory Management Scheme by a Compiler for Multicore Processor", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/141), Jan. 2009.
  36. Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara, "A Power Saving Scheme on Multicore Processors Using OSCAR API", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/145), Jan. 2009.
  37. Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Yuta Murata, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Restricted C Programs using Pointer Analysis", Technical Report of IPSJ, 2008, May. 2008. (pdf)
  38. Kaito Yamada, Masayoshi Mase, Jun Shirako, Keiji Kimura, Masayuki Ito, Toshihiro Hattori, Hiroyuki Mizuno, Kunio Uchiyama, Hironori Kasahara, "An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping", Technical Report of IPSJ, 2008, May. 2008. (pdf)
  39. Takamichi Miyamoto, Kei Tamura, Hiroaki Tano, Hiroki Mikami, Saori Asaka, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Parallelization for Multimedia Processing on Multicore Processors", Technical Report of IPSJ, 2007-ARC-175-05 (DesignGaia2007), Nov. 2007. (pdf)
  40. Hiroaki Shikano, Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2007-71), Vol. 107, No. 195, pp.11-16, Aug. 2007. (pdf)
  41. Yasutaka Wada, Akihiro Hayashi, Taketo Iyoku, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "A Hierarchical Coarse Grain Task Static Scheduling Scheme on a Heterogeneous Multicore", Technical Report of IPSJ, 2007-ARC-174-17(SWoPP2007), Aug. 2007. (pdf)
  42. Akihiro Hayashi, Taketo Iyoku, Ryo Nakagawa, Shigeru Matsumoto, Kaito Yamada, Naoto Oshiyama, Jun Shirako, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving for Heterogeneous Multicore Processor", Technical Report of IPSJ, 2007-ARC-174-18(SWoPP2007), Aug. 2007. (pdf)
  43. Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa, Makoto Sato, Masaki Ito, Toshihiko Odaka, Hironori Kasahara, "Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics", Technical Report of IPSJ, 2007-ARC-173-05, May. 2007. (pdf)
  44. Kiyoshi hayase, Yutaka Yoshida, Tatsuya Kamei, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara, "A 4320MIPS four Processor-core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption", Technical Report of IPSJ, 2007-ARC-173-06, May. 2007.
  45. Miura Tsuyoshi, Tomohiro Tagawa, Yusuke Muramatsu, Akinori Ikemi, Masahiro Nakagawa, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "A Local Memory Management Scheme in Multigrain Parallelizing Compiler", Technical Report of IPSJ, 2007-ARC-172-11, pp. 61--66, Mar. 2007
  46. Takamichi Miyamoto, Saori Asaka, Nobuhito Kamakura, Hiromasa Yamauchi, Masayoshi Mase, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization for Multimedia Applications on Multicore Processors", Technical Report of IPSJ, 2007-ARC-171-13, pp. 69--74, Oct. 2006 (pdf)
  47. Jun Shirako, Tomohiro Tagawa, Tsuyoshi Miura, Takamichi Miyamoto, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizaing Compiler on SMP Servers and Embedded Multicore", Technical Report of IPSJ, 2006-ARC-170-2, pp. 7--12, Nov. 2006 (pdf)
  48. Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Koji Fukatsu, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Automati Parallelization of Restricted C Ptrograms in OSCAR Compiler", Technical Report of IPSJ, 2006-ARC-170-1, pp. 1--6, Nov. 2006 (pdf)
  49. Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Masahiro Nakagawa, Yuki Suzuki, Yousuke Naito,Takamichi Miyamoto, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Local Memory Management on OSCAR Multicore", Technical Report of IPSJ, 2006-ARC-169-28, pp. 163-168, Aug. 2006 (pdf)
  50. Takamichi Miyamoto, Masahiro Nakagawa, Shoichiro Asano, Yosuke Naito, Takumi Nito, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Data Transfer Overlap of Coarse Grain Task Parallel Processing on a Multicore Processor", Technical Report of IPSJ, ARC-2006-167, HPC-2006-105 (HOKKE-2006), Feb., 2006.
  51. Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara, "Preliminary Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder", Technical Report of IPSJ, ARC-2006-166 (SHINING), Jan., 2006.
  52. Yasutaka Wada, Naoto Oshiyama, Yuki Suzuki, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "A Static Scheduling Scheme for Coarse Grain Task on a Heterogeneous Chip Multi Processor", Technical Report of IPSJ, ARC-2006-166 (SHINING), Jan., 2006.
  53. Hirofumi Nakano, Shoichiro Asano, Yosuke Naito, Takumi Nito, Tomohiro Tagawa, Takamichi Miyamoto, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara, "Data Localization on a Multicore Processor", Technical Report of IPSJ, ARC2005-165-10, Dec., 2005
  54. Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving Scheme for Homogeneous Multiprocessor", Technical Report of IPSJ, ARC2005-164-10 (SWoPP2005), Aug., 2005
  55. Akira Kuroda, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Electronic Circuit Simulation Using Code Generation Method without Array Indirect Access", Technical Report of IPSJ, ARC2005-161-1 (SHINING2005), Jan., 2005
  56. Jun Shirako, Takamichi Miyamoto, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on Shared Memory Multiprocessor Serers", Technical Report of IPSJ, ARC2005-161-5 (SHINING2005), Jan., 2005
  57. Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallel Processing for MPEG2 Encoding on OSCAR Chip Multiprocessor", Technical Report of IPSJ, ARC2004-160-10, Dec., 2004
  58. Yasutaka Wada, Jun Shirako, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara, "Evaluation of Multigrain Parallelism on OSCAR Chip Multi Processor", Technical Report of IPSJ, ARC2004-159-11 (SWoPP2004), Aug., 2004.
  59. Hirofumi Nakano, Yosuke Naito, Takahisa Suzuki, Takeshi Kodaka, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara, "Data Localization using Data Transfer Unit on OSCAR Chip Multiprocessor", Technical Report of IPSJ, ARC2004-159-20 (SWoPP2004), Aug., 2004.
  60. Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallel Processing on MPEG2 Encoding for OSCAR Chip Multiprocessor", Technical Report of IPSJ, ARC2003-154-10 (SWoPP2003), Aug., 2003.
  61. Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara, "Data Localization Scheme using Static Scheduling on Chip Multiprocessor", Technical Report of IPSJ, ARC2003-154-14 (SWoPP2003), Aug., 2003.
  62. Takamichi Miyamoto, Takahiro Yamaguchi, Takao Tobita, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara, "The Data Prefetching of Coarse Grain Task Parallel Processing on Symmetric Multi Proc essor Machine", Technical Report of IPSJ, ARC2003-155-06, Nov., 2003. (pdf)
  63. Takeshi Kodaka, Hirohumi Nakano, Keiji Kimura and Hironori Kasahara, "Parallel Processing for MPEG2 Encoding using Data Localization", Technical Report of IPSJ, ARC2004-156-3, Feb., 2004. (pdf)
  64. Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara, "Data Localization using Coarse Grain Task Parallelism on Chip Multiprocessor", Technical Report of IPSJ, ARC2003-151-3 (SHINING2003), Jan., 2003. (pdf)
  65. Keiji Kimura, Takeshi Kodaka, Motoki Obata, Hironori Kasahara, "Multigrain Parallel Processing on OSCAR Chip Multiprocessor", Technical Report of IPSJ, ARC2002-150-7, Nov, 2002. (pdf)
  66. Takeshi Kodaka, Takahisa Suzuki, Keiji Kimura, Hironori Kasahara, "Multigrain Parallel Processing on Motion Vector Estimation for Single Chip Multiprocessor" Technical Report of IPSJ, ARC2002-150-6, Nov, 2002.
  67. Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Motoki Obata, Hironori Kasahara, "Evaluation of Overhead with Coarse Grain Task Parallel Processing on SMP Machines", Technical Report of IPSJ, ARC2002-148-3, May., 2002. (pdf)
  68. T. Uchida, T. Kodaka, K. Kimura, H. Kasahara, "Multigrain Parallel Processing on Single Chip Multiprocessor" Technical Report of IPSJ, ARC2002-146-3, Feb., 2002. (pdf)
  69. T. Kodaka, T. Uchida, K. Kimura, H. Kasahara, "Multigrain Parallel Processing for JPEG Encoding Program on an OSCAR type Single Chip Multiprocessor" Technical Report of IPSJ, ARC2002-146-4, Feb., 2002. (pdf)
  70. T. Kodaka, N. Miyashita, K. Kimura, H. Kasahara, "Near Fine Grain Parallel Processing on Multimedia Application for Single Chip Multiprocessor", Technical Report of IPSJ, ARC2001-144-11, Aug., 2001. (pdf)
  71. H. Nakano, K. Ishizaka, M. Obata, K. Kimura, H. Kasahara, "A Static Scheduling Scheme for Coarse Grain Tasks considering Cache Optimization on SMP", Technical Report of IPSJ, ARC2001-144-12, Aug., 2001. (pdf)
  72. K. Kimura, T. Uhida, T. Kato, H. Kasahara, "Processor Core Architecture of Single Chip Multiprocessor for Near Fine Grain Parallel Processing", Technical Report of IPSJ, ARC-139-16, Aug., 2000. (pdf)
  73. K. Kimura, K. Manaka, W. Ogata, M. Okamoto, H. Kasahara, "Performance Evaluation of Near Fine Grain Parallel Processing on the Single Chip Multiprocessor", Technical Report of IPSJ, ARC134-5, Aug., 1999 (pdf)
  74. K. Iwai, M. Obata, K. Kimura, H. Amano, H. Kasahara, "Memory access analyzer for a Multi-grain parallel processing", Technical Report of IEICE, CPSY99-62, Aug., 1999
  75. H. Kasahara, W. Ogata, K. Kimura, M. Obata, T. Tobita, D. Inaishi, "A Multigrain Parallelizing Compiler and Its Architectural Support", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD98-10, CPSY98-10, FTS98-10), Apr. 1998.
  76. K. Kimura, W. Ogata, M. Okamoto, H. Kasahara, "Multigrain parallel Processing on the Single Chip Multiprocessor", Technical Report of IPSJ, ARC98-130-5, Aug., 1998. (pdf)
  77. M. Obata, G. Matsui, H. Matsuzaki, K. Kimura, D. Inaishi, Y. Ujigawa, T. Yamamoto, M. Okamoto, H. Kasahara, "Evaluation of Multigrain Parallelism using OSCAR FORTRAN Compiler", Technical Report of IPSJ, ARC-130-3, Aug., 1998.
  78. D. Inaishi, K. Kimura, K. Fujimoto, W. Ogata, M. Okamoto, H. Kasahara, "A Cache Optimization with Earliest Executable Condition Analysis", Technical Report of IPSJ, ARC-130-6, Aug., 1998.
  79. K. Kimura, S. Hashimoto, M. Kogou, W. Ogata, H. Kasahara, "A Macro Task Dynamic Scheduling Algorithm with Overlapping of Task Processing and Data Transfer", Technical Report of IEICE, CPSY97-40, Aug.1997.
  80. K. Iwai, T. Fujiwara, T. Morimura, H. Amano, K. Kimura, W. Ogata, H. Kasahara, "Multi-processor system for Multi-grain Parallel Processing", Technical Report of IEICE, CPSY97-46, Aug.1997.
  81. W. Ogata, T. Yamamoto, M. Mizuno, K. Kimura, H. Kasahara, "Implementation of FPGA Based Architecture Test Bed For Multi Processor System", IPSJ SIG Notes, 98-ARC-128-14, HPC70-14 Mar. 1998.

Annual Convention

  1. Kazuhisa Ishizaka, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara, "Evaluation of OSCAR Multigrain Automatic Parallelizing Compiler on IBM pSeries 690", Proc. 66th Annual Convention IPSJ, Mar., 2004 (pdf)
  2. H. Nakano, K. Ishizaka, M. Obata, K. Kimura, H. Kasahara, "A Static Scheduling Method for Coarse Grain Tasks considering Cache Optimization on Multiprocessor Systems", Proc. 62th Annual Convention IPSJ 4R-02, Mar., 2001.
  3. T. Kodaka, K. Kimura, N. Miyashita, H. Kasahara, "Near Fine Grain Parallel Processing on Multimedia Application for Single Chip Multiprocessor", Proc. 62th Annual Convention IPSJ 3P-08, Mar., 2001.
  4. N. Matsumoto, K. Kimura, H. Kasahara, "Performance Evaluation of Single Chip Multiprocessor Memory Architecture for Near Fine Grain Parallel Processing", Proc. 62th Annual Convention IPSJ 4P-01, Mar., 2001.
  5. N. Miyashita, K. Kimura, T. Kodaka, H. Kasahara, "A Data Transfer Unit on the Single Chip Multiprocessor for Multigrain Prallel Processing", Proc. 62th Annual Convention IPSJ 4P-02, Mar., 2001.
  6. T. Kato, W. Ogata, K. Kimura, T. Uchida, H. Kasahara, "Performance Evaluation of Single Chip Multiprocessor for Near Fine Grain Parallel Processing", Proc. 60th Annual Convention IPSJ 4J-07, Mar., 2000.
  7. D. Inaishi, K. Kimura, K. Fujimoto, W. Ogata, M. Okamoto, H. Kasahara, "A Cache Optimization Scheme Using Earliest Executable Condition Analysis", Proc. 58th Annual Convention IPSJ 3H-07, Mar., 1999.
  8. M. Obata, G. Matsui, H. Matsuzaki, K. Kimura, D. Inaishi, Y. Ujigawa, T. Yamamoto, M. Okamoto, H. Kasahara, "Evaluation of Multi-Grain Parallelism in Scientific Programs", Proc. 56th Annual Convention IPSJ, 2E-07, Mar. 1998.
  9. K. Kimura, W. Ogata, M. Okamoto, H. Kasahara, "Single Chip Multiprocessor Architecture for Multigrain Parallel Processing", Proc. 56th Annual Convention IPSJ, 1N-03, Mar. 1998.
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